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Course Description

Data conversion is the conversion of computer data from one format to another. Throughout a computer environment, data is encoded in a variety of ways. For example, computer hardware is built on the basis of certain standards, which requires that data contains, for example, parity bit checks. Similarly, the operating system is predicated on certain standards for data and file handling. Furthermore, each computer program handles data in a different manner. Whenever any one of these variables is changed, data must be converted in some way before it can be used by a different computer, operating system or program. Even different versions of these elements usually involve different data structures.

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Course Syllabus
  • Mod-01 Lec-01 Introduction to Data Conversion
  • Mod-01 Lec-02 Sampling-1
  • Mod-01 Lec-03 Sampling-2
  • Mod-01 Lec-04 Nonidealities in Samples
  • Mod-01 Lec-05 Noise due to Sampling
  • Mod-01 Lec-06 Distortion in a Sampling Switch
  • Mod-01 Lec-07 Gate Boosted Switches-1
  • Mod-01 Lec-08 Gate Boosted Switches-2
  • Mod-01 Lec-09 Charge Injection
  • Mod-01 Lec-10 S/H Characterization - 1
  • Mod-01 Lec-11 S/H Characterization - 2
  • Mod-01 Lec-12 FFTs and Leakage
  • Mod-01 Lec-13 Spectral Windows - 1
  • Mod-01 Lec-14 Spectral Windows-2
  • Mod-01 Lec-15 ADC/DAC Definitions
  • Mod-01 Lec-16 Quantization Noise - I
  • Mod-01 Lec-17 Quantization Noise -2
  • Mod-01 Lec-18 Oversampling & Noise Shaping
  • Mod-01 Lec-19 Delta-Sigma Modulation - 1
  • Mod-01 Lec-20 Delta-Sigma Modulation - 2
  • Mod-01 Lec-21 Linearized Analysis
  • Mod-01 Lec-22 Stability of Delta Sigma Modulators
  • Mod-01 Lec-23 High Order DSMs
  • Mod-01 Lec-24 NTF Design and Tradeoffs
  • Mod-01 Lec-25 Single bit Modulators
  • Mod-01 Lec-26 Loop Filter Architectures
  • Mod-01 Lec-27 Continous-time Delta Sigma Modulation
  • Mod-01 Lec-28 Implicit Antialiasing
  • Mod-01 Lec-29 Modulators with NRZ and Impulsive DACs
  • Mod-01 Lec-30 High Order CTDSMs
  • Mod-01 Lec-31 CTDM Design
  • Mod-01 Lec-32 Excess Loop Delay (ELD)
  • Mod-01 Lec-33 ELD Compensation
  • Mod-01 Lec-34 Effect of Clock Jitter on CTDSMs - 1
  • Mod-01 Lec-36 Dynamic Range Scaling
  • Mod-01 Lec-37 Simulation of CTDSMs
  • Mod-01 Lec-38 Integrator Design-1
  • Mod-01 Lec-39 Integrator Design-2
  • Mod-01 Lec-40 Flash ADC Design
  • Mod-01 Lec-41 Latches and Metastability
  • Mod-01 Lec-42 Offset in a Latch-1
  • Mod-01 Lec-43 Offset in a Latch-2 Auto Zeroing
  • Mod-01 Lec-44 Auto Zeroing-2
  • Mod-01 Lec-45 Auto Zeroing-3
  • Mod-01 Lec-46 Autozeroing in Flash ADCs
  • Mod-01 Lec-47 Flash ADC Case Study
  • Mod-01 Lec-48 Flash ADC Case Study
  • Mod-01 Lec-49 Flash ADC in a Delta Sigma Loop
  • Mod-01 Lec-50 DAC Basics
  • Mod-01 Lec-51 Binary and Thermometer DACs
  • Mod-01 Lec-52 Segmented DACs
  • Mod-01 Lec-53 Optimal DAC Segmentation
  • Mod-01 Lec-54 DAC Nonlinearities
  • Mod-01 Lec-55 Current Steering DACs-1
  • Mod-01 Lec-56 Current Steering DACs-2
  • Mod-01 Lec-57 DAC Mismatches in DSMs
  • Mod-01 Lec-58 Calibration and Randomization
  • Mod-01 Lec-59 Dynamic Element Matching-1
  • Mod-01 Lec-60 Dynamic Element Matching-2

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